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  12 - bit, 210 ms ps txdac digital - to - analog converter data sh eet AD9742 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2002 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high performance member of pin - compatible txdac product family excellent spurious - free dynamic range performance snr at 5 mhz output, 125 msps: 70 db twos complement or straight binary data format differential current outputs: 2 ma to 20 ma power dissipation: 135 mw at 3.3 v power - down mode: 15 mw at 3.3 v on - chip 1.2 v reference cmos compatible digital interface 28- lead soic, 2 8- lead tssop, and 32 - lead lfcsp edge - triggered latches applications wideband communication transmit channel: direct if ba se stations wireless local loops digital radio links direct digital synthesis (dds) instrumentation functional block dia gram 1.2v ref reflo 3.3v r set 0.1f clock sleep 02913-b-001 refio fs adj dvdd dcom clock digital data inputs (db11?db0) 150pf 3.3v avdd acom AD9742 current source array iouta ioutb mode lsb switches segmented switches latches figure 1. general description the AD9742 1 is a 12 - bit resolution, wideband, third generation member of the txdac series of high performance, low power cmos digital - to - analog converters (dacs). the txdac fam i ly , consisting of pin - compatible 8 - , 10 - , 12 - , and 14 - bit dacs, is specifically optimized for the transmit signal path of commun i cation systems. all of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on perfo r mance, resolution, and cost. the AD9742 offers exceptional ac and dc performance while supporting up date rates up to 210 msps. the AD9742s low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to a mere 60 mw with a slight degradation in performance by lowering the full - scale cur rent output. also, a power - down mode reduces the standby power dissipation to approximately 15 mw. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. ed ge - triggered input latches and a 1.2 v temperature compe n sated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 3 v cmos logic families. product highlights 1. the AD9742 is the 12 - bit member of the pin - compatible txdac family, which offers excellent inl and dnl pe r formance. 2. data input supports twos complement or straight binary data coding. 3. high speed, single - ended cmos clock input supports 210 msps conversion rate. 4. low power: complete cmos dac function operates on 135 mw from a 2.7 v to 3.6 v single supply. the dac full - scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on- chip voltage reference: the AD9742 includes a 1.2 v temperatur e compensated band gap voltage reference. 6. industry - standard 28 - lead soic, 28 - lead tssop, and 32- lead lfcsp packages. 1 protected by u.s. patent numbers : 5, 568, 145 ; 5, 689, 257 ; and 5 , 703, 519.
AD9742 data sheet rev. c | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 dynamic specifications ............................................................... 4 digital specifications ................................................................... 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descripti ons ........................... 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 11 functional description .................................................................. 12 reference operation .................................................................. 12 refer ence control amplifier .................................................... 13 dac transfer function ............................................................. 13 analog outputs .......................................................................... 13 digital inputs .............................................................................. 14 clock input .................................................................................. 14 dac timing ................................................................................ 15 power dissipation ....................................................................... 15 applying the AD9742 ................................................................ 16 differential coupling using a transformer ............................... 16 differential coupling using an op amp ................................ 16 single - ended, unbuffered voltage output ............................. 17 single - ended, buffered voltage output configuration ........ 17 power and grounding considerations, power supply rejection ...................................................................................... 17 evaluation board ............................................................................ 19 general description ................................................................... 19 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 30 revision history 2/13 rev . b to rev. c updated format .................................................................. universal changes to figure 4 and table 6 ..................................................... 7 moved terminology section ......................................................... 11 updated outline dimensions ....................................................... 29 changes to ordering guide .......................................................... 30 6/04 rev. a to rev. b changes to the title , general description, and product highlights .......................................................................................... 1 chan ges to dynamic specifications ............................................... 4 changes to figure 6 and figure 10 ................................................. 9 changes to figure 12 to figure 15 ................................................ 10 changes to the functional description section ......................... 12 changes to the digital inputs section ......................................... 14 changes to figure 29 ...................................................................... 15 changes to figure 30 ...................................................................... 16 5/03 rev. 0 to rev. a added 32 - lead lfcsp package ....................................... universal edits to features and product highlights ...................................... 1 edits to dc specifications ................................................................ 2 edits to dynamic specifications ...................................................... 3 edits to digital specifications .......................................................... 4 edits to absolute maximum ratings , thermal characteristics, and orde ring guide .......................................................................... 5 edits to pin configuration and pin function descriptions ........ 6 edits to figure 2 ................................................................................. 7 replaced tpcs 1, 4, 7, and 8 ............................................................ 8 edits to figure 3 and functional description section .............. 10 added clock input section and figure 7 .................................... 12 edits to dac timing section ....................................................... 12 edit s to sleep mode operation section and power dissipation section .............................................................................................. 13 renumbered figure 8 to figure 26............................................... 13 added figure 11 ............................................................................. 13 added figure 27 to figure 35 ....................................................... 21 updated outline dimensions ....................................................... 26 5/02 revision 0: initial version
data sheet AD9742 rev. c | page 3 of 32 specifications dc specifications t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 1. parameter min typ max unit resolution 12 bits dc accuracy 1 integral linearity error (inl) ?2.5 0.5 +2.5 lsb differential nonlinearity (dnl) ?1.3 0.4 +1.3 lsb analog output offset error ?0.02 +0.02 % of fsr gain error (without internal reference) ?0.5 0.1 +0.5 % of fsr gain error (with internal reference) ?0.5 0.1 +0.5 % of fsr full - scale output current 2 2 20 ma output compliance range ?1 +1.25 v output resistance 100 k? output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na referen ce input input compliance range 0.1 1.25 v reference input resistance (ext. reference) 1 m? small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/c gain drift (without internal reference) 50 ppm of fsr/c gain drift (with internal reference) 100 ppm of fsr/c reference voltage drift 50 ppm/c power supply supply voltages avdd 2.7 3.3 3.6 v dvdd 2.7 3.3 3.6 v clkvdd 2.7 3.3 3.6 v analog supply current (i avdd ) 33 36 ma digital supply current (i dvdd ) 4 8 9 ma clock supply current (i clkvdd ) 5 6 ma supply current sleep mode (i avdd ) 5 6 ma power dissipation 4 135 145 mw power dissipation 5 145 mw power supply rejection ratio avdd 6 ?1 +1 % of fsr/v power supply rejection ratio dvdd 6 ?0.04 +0.04 % of fsr/v operating range ?40 +85 c 1 measured at iouta, driving a virtual ground. 2 nominal full - scale current, i outfs , is 32 times the i ref current. 3 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 4 measured at f clock = 25 msps and f out = 1 mhz. 5 measured as unbuffered voltage output with i outfs = 20 ma and 50 ? r load at iouta and ioutb, f clock = 100 msps and f out = 40 mhz. 6 5% power supply variation.
AD9742 data sheet rev. c | page 4 of 32 dynamic specificatio ns t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 ? doubly te r minated, unless otherwise noted. table 2. parameter min typ max unit dynamic performance maximum output update rate (f clock ) 210 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd ) 1 ns glitch impulse 5 pv -s ec output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 2 50 pa/ hz output noise (i outfs = 2 ma) 2 30 pa/ hz noise spectral density 3 ?152 dbm/hz ac linearity spurious - free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output 74 84 dbc ?6 dbfs output 85 dbc ?12 dbfs output 82 dbc ?18 dbfs output 76 dbc f clock = 65 msps; f out = 1.00 mhz 85 dbc f clock = 65 msps; f out = 2.51 mhz 83 dbc f clock = 65 msps; f out = 10 mhz 80 dbc f clock = 65 msps; f out = 15 m hz 75 dbc f clock = 65 msps; f out = 25 mhz 74 dbc f clock = 165 msps; f out = 21 mhz 72 dbc f clock = 165 msps; f out = 41 mhz 60 dbc f clock = 210 msps; f out = 40 mhz 67 dbc f clock = 210 msps; f out = 69 mhz 60 dbc spurious - free dyn amic range within a window f clock = 25 msps; f out = 1.00 mhz; 2 mhz span 80 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 90 dbc f clock = 65 msps; f out = 5.03 mhz; 2.5 mhz span 90 dbc f clock = 125 msps; f out = 5.04 mhz; 4 mhz s pan 90 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz ?82 ?74 dbc f clock = 50 msps; f out = 2.00 mhz ?77 dbc f clock = 65 msps; f out = 2.00 mhz ?77 dbc f clock = 125 msps; f out = 2.00 mhz ?77 dbc signal -to - noise ratio f clock = 65 msps; f out = 5 mhz; i outfs = 20 ma 78 db f clock = 65 msps; f out = 5 mhz; i outfs = 5 ma 86 db f clock = 125 msps; f out = 5 mhz; i outfs = 20 ma 73 db f clock = 125 msps; f out = 5 mhz; i outfs = 5 ma 78 db f c lock = 165 msps; f out = 5 mhz; i outfs = 20 ma 69 db f clock = 165 msps; f out = 5 mhz; i outfs = 5 ma 71 db f clock = 210 msps; f out = 5 mhz; i outfs = 20 ma 69 db f clock = 210 msps; f out = 5 mhz; i outfs = 5 ma 66 db
data sheet AD9742 rev. c | page 5 of 32 parameter min typ max unit multitone power ratio (8 t ones at 400 khz spacing) f clock = 78 msps; f out = 15.0 mhz to 18.2 mhz 0 dbfs output 65 dbc ?6 dbfs output 67 dbc ?12 dbfs output 65 dbc ?18 dbfs output 63 dbc 1 measured single - ended into 50 ? load. 2 output noise is measured with a full - scale output set to 20 ma with no conversion activity. it is a measure of the thermal noise only. 3 noise spectral density is the average noise power normalized to a 1 hz bandwidth, with the dac converting and producing an output tone. digital specificatio ns t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 3. parameter min typ max unit digital inputs 1 logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 curr ent ?10 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulse width (t lpw ) 1.5 ns clk inputs 2 input voltage range 0 3 v common - mode voltage 0.75 1.5 2.25 v differen tial voltage 0.5 1.5 v 1 includes clock p in on soic/tssop packages and clk+ pin on lfcsp package in single - ended clock input mode. 2 applicable to clk+ and clk? inputs when configured for differential or pecl clock input mode. 0.1% 0.1% t s t h t pd db0?db11 clock iouta or ioutb 02912-b-002 t lpw t st figure 2 . timing diagram
AD9742 data sheet rev. c | page 6 of 32 absolute maximum rat ings table 4. parameter with re spect to min max unit avdd acom ?0.3 +3.9 v dvdd dcom ?0.3 +3.9 v clkvdd clkcom ?0.3 +3.9 v acom dcom ?0.3 +0.3 v acom clkcom ?0.3 +0.3 v dcom clkcom ?0.3 +0.3 v avdd dvdd ?3.9 +3.9 v avdd clkvdd ?3.9 +3.9 v dvdd clkvdd ?3.9 +3.9 v clock, sleep dcom ?0.3 dvdd + 0.3 v digital inputs, mode dcom ?0.3 dvdd + 0.3 v iouta, ioutb acom ?1.0 avdd + 0.3 v refio, reflo, fs adj acom ?0.3 avdd + 0.3 v clk+, clk?, mode clkcom ?0.3 clkvdd + 0.3 v junction temperature 150 c storage temperature ?65 +150 c lead temperature (10 sec) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance thermal impedance measurements were taken on a 4 - layer board in still air, in accordance with eia/jesd51 - 7. table 5 . thermal resistance package type ja unit 28- lead soic 55.9 c/w 28 - lead tssop 67.7 c/w 32 - lead lfcsp 32.5 c/w esd caution
data sheet AD9742 rev. c | page 7 of 32 pin configuration s and function descrip tions 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 28 27 26 25 24 23 22 21 nc = no connect db7 db6 db5 db4 db3 db2 db1 (lsb) db0 nc nc clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep db8 db9 db10 (msb) db11 02912-b-003 AD9742 top view (not to scale) figure 3 . 28 - lead soic and 28 - lead tssop pin configuration 24 fs adj 23 refio 22 acom 21 iouta db5 1 db4 2 dvdd 3 20 ioutb 19 acom 18 avdd 17 avdd db3 4 db2 5 db1 6 (lsb) db0 7 nc 8 AD9742 top view (not to scale) pin 1 indicator 02912-004 notes 1. nc = no connect. 2. it is recommended th a t the exposed p ad be thermal ly connected to a copper ground plane for enhanced electrica l and therma l performance. nc 9 dcom 10 clkvdd 11 clk+ 12 clk? 13 clkcom 14 cmode 15 mode 16 32 db6 31 db7 30 db8 29 db9 27 db11 (msb) 26 dcom 25 sleep 28 db10 figure 4 . 32 - lead lfcsp pin configuration table 6 . pin function descriptions (n/a = not applicable) soic/tssop pin no. lfcsp pin no. mnemonic description 1 27 db11 most significant data bit (msb). 2 to 11 28 to 32, 1, 2, 4 to 6 db10 to db1 data bits 10 to 1. 12 7 db0 least significant data bit (lsb). 13, 14 8, 9 nc no internal connection. 15 25 sleep power - down control input. active high. contains active pull- down circuit; it may be left un terminated if not used. 16 n/a reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled ( that is , tie reflo to avdd). serves as 1.2 v reference output when internal reference activated ( that is , tie reflo to acom). requires 0.1 f capacitor to acom when internal reference activated. 18 24 fs adj full - scale current output adjust. 19 n/a nc no internal connection. 20 19, 22 acom analog common. 21 20 ioutb complementary dac current output. full - scale current when all data bits are 0s. 22 21 iouta dac current output. full - scale current w hen all data bits are 1s. 23 n/a reserved reserved. do not connect to common or supply. 24 17, 18 avdd analog supply voltage (3.3 v). 25 16 mode selects input data format. connect to dcom for straight binary, dvdd for twos complement. n/a 15 cmode clock mode selection. connect to clkcom for single - ended clock receiver (drive clk+ and float clk C ). connect to clkvdd for differential receiver. float for pecl receiver (terminations on - chip). 26 10, 26 dcom digital common. 27 3 dvdd di gital supply voltage (3.3 v). 28 n/a clock clock input. data latched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clk ? differential clock input. n/a 11 clkvdd clock supply voltage (3.3 v). n/a 14 clkcom clock common. n/a epad it is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced electric and thermal performance.
AD9742 data sheet rev. c | page 8 of 32 typical performance characteristics 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) f out (mhz) 1 10 100 02912-b-006 125msps (lfcsp) 165msps 210msps 165msps (lfcsp) 210msps (lfcsp) 125msps 65msps figure 5 . sfdr vs. f out @ 0 dbfs 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) 0 5 10 15 20 25 f out (mhz) 02912-b-009 0dbfs ?6dbfs ?12dbfs figure 6 . sfdr vs. f out @ 65 msps 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) 0 5 10 15 20 25 30 35 40 45 f out (mhz) 02912-b-012 0dbfs ?6dbfs ?12dbfs figure 7 . sfdr vs. f out @ 125 msps 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) 20 30 0 10 40 50 60 f out (mhz) 02912-b-007 0dbfs (lfcsp) 0dbfs ?6dbfs (lfcsp) ?6dbfs ?12dbfs ?12dbfs (lfcsp) figure 8 . sfdr vs. f out @ 165 msps 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) 0 10 30 20 40 50 60 70 f out (mhz) 02912-b-054 ?12dbfs (lfcsp) 0dbfs ?6dbfs (lfcsp) ?6dbfs 0dbfs (lfcsp) ?12dbfs figure 9 . sfdr vs. f out @ 210 msps 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) 0 5 10 15 20 25 f out (mhz) 02912-b-010 20ma 10ma 5ma figure 10 . sfdr vs. f out and i outfs @ 65 msps and 0 dbfs
data sheet AD9742 rev. c | page 9 of 32 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) ?25 ?20 ?15 ?10 ?5 0 a out (dbfs) 02912-b-013 65msps 210msps 210msps (lfcsp) 125msps 165msps figure 11 . single - tone sfdr vs. a out @ f out = f clock /11 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) ?25 ?20 ?15 ?10 ?5 0 a out (dbfs) 02912-b-008 165msps 65msps 165msps (lfcsp) 125msps (lfcsp) 125msps 210msps 210msps (lfcsp) figure 12 . single - tone sfdr vs. a out @ f out = f clock /5 50 55 60 65 70 75 80 snr 25 45 65 85 105 125 145 165 205185 f clock (mhz) 02912-b-011 20ma 10ma 5ma figure 13 . snr vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs 45 50 55 60 65 70 75 80 85 90 95 sfdr (dbc) ?25 ?20 ?15 ?10 ?5 0 a out (dbfs) 02912-b-014 65msps (8.3,10.3) 78msps (10.1,12.1) 125msps (16.9, 18.9) 165msps (22.6, 24.6) 210msps (29, 31) 210msps (29, 31) figure 14 . dual - tone imd vs. a ou t @ f out = f clock /7 error (lsb) ?1.0 ?0.5 0 0.5 1.0 code 1024 0 2048 3072 4096 02912-b-015 figure 15 . typical inl ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 error (lsb) code 1024 0 2048 3072 4096 02912-b-017 figure 16 . typical dnl
AD9742 data sheet rev. c | page 10 of 32 50 55 60 65 70 75 sfdr (dbc) 80 85 90 0 20 ?40 ?20 40 60 80 temperature (c) 02912-b-019 4mhz 19mhz 34mhz 49mhz figure 17 . sfdr vs. temperature @ 165 msps, 0 dbfs ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 magnitude (dbm) 1 6 11 16 21 26 31 36 frequency (mhz) 02912-b-016 f clock = 78msps f out = 15.0mhz sfdr = 79dbc amplitude = 0dbfs figure 18 . single - to ne sfdr ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 magnitude (dbm) 1 6 11 16 21 26 31 36 frequency (mhz) 02912-b-018 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz sfdr = 77dbc amplitude = 0dbfs figure 19 . dual - tone sfdr ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 magnitude (dbm) 1 6 11 16 21 26 31 36 frequency (mhz) 02912-b-020 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz f out3 = 15.8mhz f out4 = 16.2mhz sfdr = 75dbc amplitude = 0dbfs figure 20 . four - tone sfdr digital data inputs (db11?db0) 150pf 1.2v ref avdd acom reflo pmos current source array 3.3v segmented switches for db11?db3 lsb switches refio fs adj dvdd dcom clock 3.3v r set 2k? 0.1f iouta ioutb AD9742 sleep latches i ref v refio clock ioutb iouta r load 50? v outb v outa r load 50? v diff = v outa ? v outb mode 02912-b-021 figure 21 . simplified block diagram (soic/tssop packages)
data sheet AD9742 rev. c | page 11 of 32 terminology linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the ac tual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variat ion in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full - scale output as the supplies are varied from nominal to minimum and maxim um specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv -s. spurious - free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal ov er the specified ban d width. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is ex pressed as a percentage or in decibels (db). multitone power ratio the s purious - free dynamic range containing multiple carrier tones of equal amplitude. it is measured as the difference be tween the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. 150pf 1.2v ref avdd acom reflo pmos current source array segmented switches for db11?db3 lsb switches refio fs adj dvdd dcom clock 3.3v r set 2k? 0.1f dvdd dcom iouta ioutb AD9742 sleep 50? retimed clock output* latches digital data tektronix awg-2021 with option 4 lecroy 9210 pulse generator clock output 50? rohde & schwarz fsea30 spectrum analyzer mini-circuits t1-1t *awg2021 clock retimed so that the digital data transitions on falling edge of 50% duty cycle clock. 3.3v mode 50? 02912-b-005 figure 22 . basic ac characterization test set - up (soic/tssop packages)
AD9742 data sheet rev. c | page 12 of 32 functional descripti on AD9742 consists of a dac, digital control logic, and full - scale output current control. the dac contains a pmos current source array capable of providing up to 20 ma of full - scale cu r rent (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the re maining lsbs are binary weighted fractions of the middle bits current sources. implementing the middle and lower bits with current sources, instead of an r - 2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintai n the dacs high output impedance (i.e., >100 k?). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos diffe r ential current switches. the switches are based on the architecture that was pion eered in the ad9764 family, with fu r ther refinements to reduce distortion contributed by the switc h ing transient. this switch architecture also reduces various ti m ing errors and provides matching complementary drive signals to the inputs of the differenti al current switches. the analog and digital sections of the AD9742 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 v to 3.6 v range. the digital section, which is capable of operating at a rate of up to 210 msps, co n sists of edge - triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.2 v band gap voltage reference, and a reference control amplifier. the dac full - scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set , connected to the full - scale adjust ( fs adj) pin. the external resistor, in combination with both the refe r ence control a mplifier and voltage reference ,v refio , sets the reference current, i ref , which is replicated to the segmented current sources with the proper scaling factor. the full - scale current, i outfs , is 32 times i ref . reference operation the AD9742 contains an int ernal 1.2 v band gap reference. the internal reference can be disabled by raising reflo to avdd. it can also be easily overridden by an external reference with no effect on performance. refio serves as either an input or an output depending on whether the internal or an external refe r ence is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor and connect reflo to acom via a resistance less than 5 ?. the internal reference voltage will be present at refio. if the voltage at re fio is to be used anywhere else in the circuit, an external buffer ampl i fier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in f igure 23 . 150pf 1.2v ref avdd reflo current source array 3.3v refio fs adj 2k? 0.1f AD9742 additional load optional external ref buffer 02912-b-022 f igure 23 . internal reference configuration an external reference can be applied to refio, as shown in figure 24 . the external reference may provide either a fixed reference voltage to enhance accuracy and d rift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal refe r ence is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference. 150pf 1.2v ref avdd reflo current source array refio fs adj r set AD9742 external ref i ref = v refio /r set avdd reference control amplifier v refio 3.3v 02912-b-023 figure 24 . external reference configuration
data sheet AD9742 rev. c | page 13 of 32 reference control am plifier the AD9742 contains a control amplifier that is used to regulate the full - scale output current, i outfs . the control amplifier is configu red as a v - i converter, as shown in figure 24 , so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs , as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of ioutfs over a 2 ma to 20 ma range by setting iref between 62.5 a and 625 a. the wide adjustment span of ioutfs provides several benefits. the first relates directly to the power dissipation of the AD9742, which is proportional to ioutfs (see the power dissipation section). the second relates to the 20 db adjustment, which is useful for syst em gain control pu r poses. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency small signal multiplying applications. dac transfer functio n both dacs in the AD9742 provide complementary cu rrent outputs, iouta and ioutb . iouta provides a near full - scale current output, i outfs , when all bits are high (i.e., dac code = 4095), while ioutb , the complementary output, provides no current. the current output appearing at iouta and ioutb is a functi on of both the input code and i outfs and can be ex pressed as: ( ) outfs i codedac iouta = 4096/ (1) ( ) outfs i codedac ioutb ?= /4096 4095 (2) where dac code = 0 to 4095 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , w hich is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as: ref outfs i i = 32 (3) where set refio ref rvi / = (4) the two current outputs will typically drive a resistive load di rectly or via a transf ormer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by iouta or ioutb as would be the ca se in a doubly terminated 50 ? or 75 ? cable. the single - ended voltage output appearing at the iouta and ioutb nodes is simply load outa r iouta v = (5) load outb r ioutb v = (6) note that the full - scale value of v outa and v outb should not exceed the s pecified output compliance range to maintain spec i fied distortion and linearity performance. ( ) load diff r ioutb iouta v ?= (7) substituting the values of iouta , ioutb , i ref , and v diff can be expressed as: ( ) { } ( ) refio set load diff vrr codedac v ? = /32 4096/4095 2 (8) equations 7 and 8 highlight s ome of the advantages of opera t ing the AD9742 differentially. first, the differential operation helps cancel common - mode error sources associated with iouta and ioutb, such as noise, distortion, and dc offsets. second, the differential code - dependent current and subsequent voltage, v diff , is twice the value of the single - ended voltage ou t put (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single - ended (v outa and v outb ) or diff erential output (v diff ) of the AD9742 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship, as shown in equation 8. analog outputs the complementary current outputs in each dac, iouta, and iou tb may be configured for single - ended or differential operation. iouta and ioutb can be converted into compl e- mentary single - ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function se c tion by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single- ended voltage via a transformer or differential amplifier configuration. the ac performance of the AD9742 is optimum and specified using a differential transformer - coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. the distortion and noise performance of the AD9742 can be enhanced when it is configured for differential operation. the commo n- mode error sources of both iouta and ioutb can be significantly reduced by the common - mode rejection of a transformer or differential amplifier. these common - mode error sources include even - order distortion products and noise. the enhancement in distorti on performance becomes more significant as the frequency content of the reconstructed wav e form increases and/or its amplitude decreases. this is due to the first - order cancellation of various dynamic common - mode distortion mechanisms, digital feedthrough, and noise. performing a differential - to -single- ended conversion via a transformer also provides the ability to deliver twice the reco n structed signal power to the load (assuming no source termin a tion). since the output currents of iouta and ioutb are compl ementary, they become additive when processed di f ferentially. a properly selected transformer will allow the AD9742 to provide the required power and voltage levels to different loads.
AD9742 data sheet rev. c | page 14 of 32 the output impedance of iouta and ioutb is determined by the equivale nt parallel combination of the pmos switches asso ciated with the current sources and is typically 100 k ? in para l lel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a vi r tual ground via an i - v op amp configuration will result in the opt i mum dc linearity. note that the inl/dnl specifications for the AD9742 are measured with iouta maintained at a vi r tual ground via an op amp. iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achie ve optimum performance. the negative output compliance range of ?1 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a brea k down of the output stage and affect the reliability of the AD9742. the positive output compliance range is slightly dependent on the full - sca le output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 20 ma to 1 v for an i outfs = 2 ma. the optimum distortion performance for a single - ended or differential output is achieved when the maximum full -scale signal at iouta a nd ioutb does not exceed 0.5 v. digital inputs the AD9742 digital section consists of 12 input bit channels and a clock input. the 12 - bit parallel data inputs follow stan d ard positive binary coding, where db11 is the most significant bit ( msb) and db0 is t he least significant bit (lsb). iouta produces a full - scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full - scale current split between the two outputs as a function of the input code. dvdd digital input 02912-b-024 figure 25 . equivalent digital input the digital interface is implemented using an edge - triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 210 msps. the clock can be operated at any duty cycle that meets the specified latch pulse width. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion pe r formance. best performance is typically achieved when the input data trans i tions on the falling edge of a 50% duty cycle clock. clock input soic/tssop packages the 28 - lead package options have a single - ended clock input ( clock) that must be driven to rail - to - rail cmos levels. the quality of the dac output is directly related to the clock quality, and jitter is a key concern. any noise or jitter in the clock will translate directly into the dac output. optimal performance w ill be achieved if the clock input has a sharp rising edge, since the dac latches are positive edge triggered. lfcsp package a configurable clock input is available in the lfcsp package, which allows for one single - ended and two differential modes. the mod e selection is controlled by the cmode input, as summarized in table 7 . connecting cmode to clkcom se lects the single - ended clock input. in this mode, the clk+ input is driven with rail - to - rail swings and the clk? input is left flo ating. if cmode is connected to clkvdd, the differe n tial receiver mode is selected. in this mode, both inputs are high impedance. the final mode is selected by floating cmode. this mode is also differential, but internal terminations for positive emitter -c oupled logic (pecl) are activated. there is no significant performance difference between any of the three clock input modes. table 7 . clock mode selection cmode pin clock input mode clkcom single - ended clkvdd differential float pecl the single - ended input mode operates in the same way as the clock input in the 28 - lead packages, as described previously. in the differential input mode, the clock input functions as a high impedance differential pair. the common - mode level o f the clk+ and clk ? inputs can vary from 0.75 v to 2.25 v, and the differential voltage can be as low as 0.5 v p - p. this mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave int o a single - ended square wave internally. the final clock mode allows for a reduced external component count when the dac clock is distributed on the board using pecl logic. the internal termination configuration is shown in figure 26 . these termination resistors are untrimmed and can vary up to 20%. however, matching between the resistors should generally be better than 1%. clk+ to dac core clk? v tt = 1.3v nom 50? 50? AD9742 clock receiver 02912-b-025 figure 26 . clock termination in pecl mode \
data sheet AD9742 rev. c | page 15 of 32 dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relatio n ship between the position of the clock edges and the time at which the input data changes. the AD9742 is rising edge triggered, and so exhibits dynamic performance sensitivity when the data tra nsition is close to this edge. in general, the goal when applying the AD9742 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 27 shows the rel ationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock plac e ment, while at higher rates, more care must be taken. ?3 ?2 2 ?1 0 1 65 75 ns db 3 55 45 35 60 70 50 40 50mhz sfdr 20mhz sfdr 50mhz sfdr 02912-b-026 figure 27 . sfdr vs. clock placement @ f out = 20 mhz and 50 mhz sleep mode operation the AD9742 has a power - down function that turns off the ou t put current and reduces the supply current to less than 6 ma over the specified supply range of 2.7 v to 3.6 v and temper a ture range. this mode c an be activated by applying a logic le v el 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 ? avdd. this digital input also contains an active pull - down circuit that ensures that the AD9742 remains enabled if this input is left disconnected . the AD9742 takes less than 50 ns to power down and approximately 5 s to power back up. power dissipation th e power dissipation, p d , of the AD9742 is dependent on se v eral factors that include: ? the power supply voltages (avdd, clkvdd, and dvdd) ? the full -s cale current output i outfs ? the update rate f clock ? the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in figure 28 , and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply dvdd. figure 29 shows i dvdd as a funct ion of full - scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 3.3 v. i outfs (ma) 35 0 2 i avdd (ma) 30 25 20 15 10 4 6 8 10 12 14 16 18 20 02912-b-027 figure 28 . i avdd vs. i outfs ratio (f out /f clock ) 20 0.01 1 0.1 i dvdd (ma) 18 16 14 12 10 8 6 4 2 0 165msps 125msps 65msps 02912-b-028 210msps figure 29 . i dvdd vs. ratio @ dvdd = 3.3 v 0 50 250 100 150 200 0 2 4 6 8 12 10 f clock (msps) i clkvdd (ma) diff pecl se 02912-b-029 figure 30 . i clkvdd vs. f clock and clock mode
AD9742 data sheet rev. c | page 16 of 32 applying the AD9742 output configurations the following sections illustrate some typical output configur a tions for the AD9742. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may co n sist of either an rf transformer or a differential op amp configuration. the transformer configuration provides opt i mum high frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc co u pling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. a single - ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb are connected to an appropr i ately sized load resistor, r load , referred to acom. this config u ration may be more suitable for a single - supply system requiring a dc - coupled, ground - referred output voltage. alte r natively, an amplifier could be configured as an i - v converter, thus conver t ing iouta or ioutb into a negative unipolar voltage. this co n figuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential couplin g using a tran s former an rf transformer can be used to perform a differential - to - single - ended signal conversion, as shown in figure 31 . a diffe r entially coupled transformer output provides the optimum distortion performance for output signals whose spectral co n tent lies within the transformers pass band. an rf transformer, such as the mini - circuits t1 C 1t, provides excellent rejection of common - mode distortion ( that is , even - order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different i mpedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load AD9742 mini-circuits t1-1t optional r diff iouta ioutb 22 21 02912-b-030 figure 31 . differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages ap pearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compl iance range of the AD9742. a diffe r ential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approximat e ly half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential - to - singl e- ended conversion, as shown in figure 32 . the AD9742 is configured with two equal load resistors, r load , of 25 ?. the diffe r ential voltage developed across iouta and ioutb is converted to a single- ended signal via the differential op amp configur a tion. an optional capacitor can be installed across iouta and ioutb , forming a real pole in a low - pass filter. the addition of this capacitor also enhances the op amps distortion perfor m ance by preventing the dacs high sl ewing output from ove r loading the op amps input. AD9742 iouta ioutb c opt 500? 225? 225? 500? 25? 25? ad8047 02912-b-031 22 21 figure 32 . dc differential coupling using an op amp the common - mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differen tial op amp circuit using the ad8047 is configured to pr o vide some additional signal gain. the op amp must operate off a dual supply since its output is approximately 1 v. a high speed a m plifier capable of preserving the differential performance of the ad 9742 while meeting other system level objectives (e.g., cost or power) should be selected. the op amps differential gain , gain setting resistor values, and full - scale output swing capabilities should all be considered when optimizing this ci r cuit. the di fferential circuit shown in figure 33 provides the nece s sary level shifting required in a single - supply system. in this case, avdd, which is the positive analog supply for both the AD9742 and the op amp, is also use d to level shift the di f ferential output of the AD9742 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. AD9742 iouta ioutb c opt 500? 225? 225? 1k? 25? 25? ad8041 1k? avdd 22 21 02912-b-032 figure 33 . single - supply dc differential coupled circuit
data sheet AD9742 rev. c | page 17 of 32 single - ended, unbuffered vo ltag e output figure 34 shows the AD9742 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly term i nated 50 ? cable since the nominal full - scale current, i outfs , of 20 ma flows through the equivalent r load of 25 ?. in this case, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be co n nected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one additional consideration in this mode i s the integral nonlinearity (inl), discussed in the analog outputs section. for optimum inl performance, the single - ended, b uffered voltage output configuration is su g gested. AD9742 iouta ioutb 50 ? 25? v outa = 0v to 0.5v i outfs = 20ma 50? 22 21 02912-b-033 figure 34 . 0 v to 0.5 v unbuffered voltage output single - ended, buffered volt age output configuration figure 35 shows a buffered single - ended output conf iguration in which the op amp u1 performs an i - v conversion on the AD9742 output current. u1 maintains iouta (or ioutb) at a virtual ground, minimizing the nonlinear output impedance effect on the dacs inl performance as described in the analog outputs section. although this single - ended configur a tion typically provides the best dc linearity performance, its ac di s tortion performance at higher dac update rates may be limited by u1s slew rate capabilities. u1 provid es a negative unipolar output voltage, and its full - scale output voltage is si m ply the product of r fb and i outfs . the full - scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortio n performance may result with a reduced i outfs since u1 will be r e quired to sink less signal current . AD9742 iouta ioutb c opt 200? u1 v out = i outfs r fb i outfs = 10ma r fb 200? 22 21 02912-b-034 figure 35 . unipolar buffered voltage output power and grounding considerations, power supply rejecti on many applications s eek high speed and high performance under less than ideal operating conditions. in these application circuits , the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for dev ice selection, placement, and rou t ing as well as power supply bypassing and grounding to ensure optimum performance. figure 40 to figure 43 illustrate the recommended printed circuit board ground, power, an d signal plane layouts implemented on the AD9742 eval u ation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. th is is referred to as the power supply rejection ratio (psrr). for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dacs full - scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is ge n erated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr versus frequency of the AD9742 avdd supply over this frequency range is shown in figure 36 . frequency (mhz) 85 40 12 6 8 10 0 psrr (db) 80 75 70 65 60 55 50 2 4 45 02912-b-035 figure 36 . power supply rejection ratio (psrr) note that the ratio in figure 36 is calculated as amps out/volts in. noise on the analo g power supply has the effect of modula t ing the internal switches, and therefore the output current. the voltage noise on avdd, therefore, will be added in a nonlinear manner to the desired iout. due to the relative different size of these switches, the ps rr is very code dependent. this can pr o duce a mixing effect that can modulate low frequency power supply noise to higher frequencies. worst - case psrr for either one of th e differential dac outputs will occur when the full - scale current is directed toward t hat output. as a result, the psrr measurement in figure 36 represents a worst - case cond i tion in which the digital inputs remain static and the full - scale output current of 20 ma is directed to the dac output being measured.
AD9742 data sheet rev. c | page 18 of 32 an e xample serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simpli c itys sake (ignoring harmonics), all of this noise is concentrated at 2 50 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dacs full - scale current, i outfs , one must determine the psrr in db using figure 36 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 36 by the scaling factor 20 ? log (r load ). for instance, if r load is 50 ? , the psrr is reduced by 34 db (i.e., psrr of the dac at 250 khz, which is 85 db in figure 36 , b e comes 51 db v out /v in ). proper grounding and decoupling should be a primar y obje c tive in any high speed, high resolution system. the AD9742 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be dec oupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single 3.3 v supply for bot h the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 37 . the circuit co n sists of a differential lc filter with separate power supply and return lines. lower noi se can be attained by using low esr type electrolytic and tantalum capacitors. 100f elect. 0.1f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads avdd acom 10f?22f tant. 02912-b-036 figure 37 . differential lc filter for single 3.3 v applications
data sheet AD9742 rev. c | page 19 of 32 evaluation board general description the txdac family evaluation boards allow for e asy setup and testing of any txdac product in the soic and lfcsp packa g es . careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the AD9742 eas i ly and effectively in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the AD9742 in various configurations. possible output configurations include transformer coupled, resistor terminated, and si n gle and differential outputs. the di gital inputs are designed to be driven from various word generators, with the on - board option to add a resistor network for proper load termination. provisions are also made to operate the AD9742 with either the internal or external reference or to exercise the power - down fe a ture. 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp5 opt 1 dcom 16 1 rp3 22 ? db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x db0x 15 2 rp3 22 ? 14 3 rp3 22 ? 13 4 rp3 22 ? 12 5 rp3 22 ? 11 6 rp3 22 ? 10 7 rp3 22 ? 9 8 rp3 22 ? 16 1 rp4 22 ? 15 2 rp4 22 ? 14 3 rp4 22 ? 13 4 rp4 22 ? 12 5 rp4 22 ? 11 6 rp4 22 ? 9 8 rp4 22 ? 10 7 rp4 22 ? ckext ckextx 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp6 opt 1 dcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp1 opt 1 dcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp2 opt 1 dcom 2 1 db13x 4 3 db12x 6 5 db11x 8 7 db10x 10 9 db9x 12 11 db8x 14 13 db7x 16 15 db6x 18 17 db5x 20 19 db4x 22 21 db3x 24 23 db2x 26 25 db1x 28 27 db0x 30 29 32 31 34 33 ckextx 36 35 38 37 40 39 jp3 j1 ribbon tb1 1 tb1 2 l2 bead c7 0.1f tp4 blk + dvdd tp7 c6 0.1f c4 10f 25v blk blk tp8 tp2 red tb1 3 tb1 4 l3 bead c9 0.1f tp6 blk + avdd tp10 c8 0.1f c5 10f 25v blk blk tp9 tp5 red 02912-b-037 figure 38 . soic evaluation board power supply and digital inputs
AD9742 data sheet rev. c | page 20 of 32 r6 opt s2 iouta 2 a b jp10 1 3 ix r11 50? c13 opt jp8 iout s3 4 5 6 3 2 1 t1 t1-1t jp9 c12 opt r10 50? s1 ioutb 1 2 3 a b jp11 iy 1 ext 2 3 int a b jp5 ref + + c14 10f 16v c16 0.1f c17 0.1f avdd dvdd ckext db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 avdd c15 10f 16v c18 0.1f c19 0.1f cut under dut jp6 jp4 r5 opt dvdd r4 50? clock s5 clock tp1 wht dvdd avdd dvdd r2 10k? jp2 mode tp3 wht ref c2 0.1f c1 0.1f c11 0.1f r1 2k? 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u1 AD9742 sleep tp11 wht r3 10k? clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 avdd 02912-b-038 figure 39 . soic evaluation board output signal conditioning
data sheet AD9742 rev. c | page 21 of 32 02912-b-039 figure 40 . so ic evaluation board primary side 02912-b-040 figure 41 . soic evaluation board secondary side
AD9742 data sheet rev. c | page 22 of 32 02912-b-041 figure 42 . soic evaluation board ground plane 02912-b-042 figure 43 . soic evaluation board power plane
data sheet AD9742 rev. c | page 23 of 32 02912-b-043 figure 44 . soic evaluation board assembly primary side 02912-b-044 figure 45 . soic evaluation board assembly secondary side
AD9742 data sheet rev. c | page 24 of 32 cvdd red tp12 bead tb1 1 tb1 2 c7 0.1f c9 0.1f c3 0.1f blk tp2 tp4 tp6 blk blk c6 0.1f c8 0.1f c10 0.1f c2 10f 6.3v c4 10f 6.3v c5 10f 6.3v l1 dvdd red tp13 bead tb3 1 tb3 2 l2 avdd red tp5 bead tb4 1 tb4 2 l3 j1 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 header straight up male no shroud jp3 ckextx ckext ckextx r21 100? r24 100? r25 100? r26 100? r27 100? r28 100? db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 22? 16 22? 15 22? 14 22? 13 22? 12 22? 11 22? 10 22? 9 22? 16 22? 15 22? 14 22? 13 22? 12 22? 11 22? 10 22? 9 r20 100? r19 100? r18 100? r17 100? r16 100? r15 100? r4 100? r3 100? 1 rp3 2 rp3 3 rp3 4 rp3 5 rp3 6 rp3 7 rp3 8 rp3 1 rp4 2 rp4 3 rp4 4 rp4 5 rp4 6 rp4 7 rp4 8 rp4 02912-b-045 figure 46 . lfcsp evaluation board schematic power supply and di gital inputs
data sheet AD9742 rev. c | page 25 of 32 c19 0.1 cvdd cvdd db8 db9 db10 db11 clkb db5 dvdd db6 db7 clk db0 db1 db2 db3 db4 db13 db12 iout avdd dvdd cvdd avdd db8 db9 db10 db11 ib fs adj clkb db5 dvdd db6 db7 clk cvdd dcom db0 db1 db2 db3 db4 dcom1 db13 acom1 avdd acom ia refio avdd1 sleep db12 ccom cmode mode cmode mode t1 ? 1t t1 jp8 jp9 4 3 2 1 5 6 agnd: 3, 4, 5 s3 50? r11 c13 28 25 17 23 21 22 18 19 27 26 24 20 29 30 31 32 dnp dnp c12 c11 0.1f c17 0.1f c19 0.1f c32 0.1f 10k? r30 10k? r29 u1 ad9744lfcsp 14 5 6 7 8 9 10 11 12 1 2 3 4 13 15 16 wht tp1 wht tp11 jp1 0.1% 2k? r1 r10 50? wht tp3 tp7 wht sleep 02912-b-046 figure 47 . lfcsp evaluation board schematic output signal conditioning u4 u4 jp2 agnd: 5 cvdd: 8 4 3 6 cvdd: 8 c35 0.1f c20 10 f 16v s5 agnd: 3, 4, 5 c34 0.1f ckext clk clkb r5 120 ? r2 120 ? r6 50 ? cvdd agnd: 5 2 1 7 cvdd 02912-b-047 figure 48 . lfcsp evaluation board schematic clock input
AD9742 data sheet rev. c | page 26 of 32 02912-b-048 figure 49 . lfcsp evaluat ion board layout primary side 02912-b-049 figure 50 . lfcsp evaluation board layout secondary side
data sheet AD9742 rev. c | page 27 of 32 02912-b-050 figure 51 . lfcsp evaluation board layout ground plane 02912-b-051 figure 52 . lfcsp evaluation board layout power plane
AD9742 data sheet rev. c | page 28 of 32 02912-b-052 figure 53 . lfcsp evaluation board layout assembly primary side 02912-b-053 figure 54 . lfcsp evaluation board layout assembly secondary side
data sheet AD9742 rev. c | page 29 of 32 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 55 . 28 - lead thin shrink small outline package [tssop] (ru - 28) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ae 18.10 (0.7126) 17.70 (0.6969) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 28 15 14 1 1.27 (0.0500) bsc 06-07-2006-a figure 56 . 28 - lead standard small outline package [soic _w ] wide body (r w- 28) dimensions shown in millimeters and (inches)
AD9742 data sheet rev. c | page 30 of 32 compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 57 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9742ar ?40c to +85c 28- lead standard small outline package [soic] rw- 28 AD9742arz ?40c to +85c 28- lead standard small outline package [soic] rw- 28 AD9742arzrl ?40c to +85c 28- lead standard small outline package [soic] rw- 28 AD9742aru ?40c to +85 c 28- lead thin shrink small outline package [tssop] ru -28 AD9742arurl7 ?40c to +85c 28- lead thin shrink small outline package [tssop] ru -28 AD9742aruz ?40c to +85c 28- lead thin shrink small outline package [tssop] ru -28 AD9742aruzrl7 ?40c to +85c 28 - lead thin shrink small outline package [tssop] ru - 28 AD9742acpz ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32 -7 AD9742acpzrl7 ?40c to +85c 32- lead lead frame chip scale package [lfcsp_wq] cp -32 -7 AD9742 -eb z evaluatio n board [soic] AD9742acp - pcb z evaluation board [ lfcsp ] 1 z = rohs compliant part.
data sheet AD9742 rev. c | page 31 of 32 notes
AD9742 data sheet rev. c | page 32 of 32 notes ? 2002 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02912 -0- 2/13(c)


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